View MT28F1284W18_4105491.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
FLASH MEMORY
Features
Dedicated commands to decrease programming times for both in-factory and in-system operations Fast programming algorithm (FPA) for fast PROGRAM operation 16-word page Flexible 8Mb multipartition architecture Single word (16-bit) data bus Support for true concurrent operation with zero latency Basic configuration: * 135 individually programmable/erasable blocks * 16 partitions (8Mb each for code and data storage) Operating Voltage * VCC = 1.70V (MIN)-1.95V (MAX) * VCCQ = 1.70V (MIN)-2.24V (MAX) VPP = 1.8V (TYP) for in-system PROGRAM/ERASE * 12V 5% (HV) VPP tolerant (factory programming compatibility) Random access time: 60ns @ 1.70V VCC Burst mode read access * MAX clock rate: 66 MHz (tCLK = 15ns) * MAX clock rate: 54 MHz (tCLK = 18.5ns) * Burst latency 60ns @1.70V VCC and 66 MHz * 4 word, 8 word, 16 word, and continuous burst modes * tACLK: 14ns @ 1.70V VCC and 54 MHz * tACLK: 11ns @ 1.70V VCC and 66 MHz Page mode read access * Interpage read access: 60ns @ 1.70V VCC * Intrapage read access: 15ns @ 1.70V VCC Low power consumption (VCC = 1.95V) * Burst read @ 66 MHz <10mA (TYP) * Standby < 50A(TYP) * Automatic power save (APS) Enhanced program and erase suspend options * ERASE-SUSPEND-to-READ within same partition * PROGRAM-SUSPEND-to-READ within same partition * ERASE-SUSPEND-to-PROGRAM within same partition Dual 64-bit chip protection registers for security purposes Cross-compatible command support * Extended command set * Common flash interface Programmable WAIT# configuration Clock suspend 100,000 ERASE cycles per block
MT28F1284W18
1.8V Low Voltage, Extended Temperature Figure 1: 56-Ball VFBGA
1 A B C D E F G
A11
2
A8
3
VSS
4
VCC
5
VPP
6
A18
7
A6
8
A4
A12
A9
A20
CLK
RST#
A17
A5
A3
A13
A10
A21
ADV#
WE#
A19
A7
A2
A15
A14
WAIT#
A16
DQ12
WP#
A22
A1
VCCQ
DQ15
DQ6
DQ4
DQ2
DQ1
CE#
A0
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
OE#
DQ7
VSSQ
DQ5
VCC
DQ3
VCCQ
DQ8
VSSQ
Top View
NOTE: 1. See Table 3 for ball descriptions. 2. See Figure 35 for mechanical drawing.
Options
Timing * 60ns access * 70ns access Burst Frequency * 54 MHz * 66 MHz1 Boot Block Configuration * Top * Bottom Package * 56-ball VFBGA (Standard) 7 x 8 ball grid * 56-ball VGBGA (Lead-free) 7 x 8 ball grid2 Operating Temperature Range * Extended (-40C to +85C)
NOTES: 1. Contact factory for availability. 2. Contact factory for details. Part Number Example:
Marking
-60 -70 5 6 T B FQ BQ
ET
MT28F1284W18FQ-705 TET
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(c)2003 Micron Technology, Inc. All rights reserved.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Architecture and Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Command State Machine (CSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Command State Machine Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Clear Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Device Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Asynchronous/Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Read Configuration Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 WAIT# Signal Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 WAIT# Signal Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Hold Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 WAIT# Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Burst Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Programming Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Conventional Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Fast Programming Algorithm (FPA) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ERASE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PROGRAM SUSPEND, PROGRAM RESUME, ERASE SUSPEND, ERASE RESUME Commands . . . . . . . . . . . . . . . .27 READ-While-PROGRAM/ERASE Concurrency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Locked Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Reading the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Programming the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Locking the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 VPP/VCC Program and Erase Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Automatic Power Save (APS) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Electrical Specificatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Appendix A: CFI Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Appendix B: CSM Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: 56-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Partition Boundary Wrapping (Bottom Boot Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Hold Data Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Conventional Word Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Fast Programming Algorithm (FPA) Flowchart (in-factory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Block Erase Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Program Suspend/Program Resume Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Erase Suspend/Erase Resume Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Block Locking State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Locking Operations Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Protection Register Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 VCC and VPP at Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Reset Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Output Load Circuit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Single Asynchronous READ Operation (Nonlatched Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Latched Asynchronous READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Single Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 READ Timing Parameters for Four-Word BURST Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 WAIT# Functionality for End-of-Word Line (EOWL) Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 WAIT# Signal in Burst Non-READ ARRAY Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 WAIT# Signal in Asynchronous READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Two-Cycle WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Asynchronous READ-to-WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 WRITE-to-Asynchronous-READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Burst READ-to-WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Write-to-BURST READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 56-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Cross-Reference for Abbreviated Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Command Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Command Codes and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Status Register SR7 and SR0 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Clock Frequency vs. First Access Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Simultaneous Operations Allowed in the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Block Locking State Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Write Protection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Device Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 VPP Range (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Reset Parameter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 ERASE and PROGRAM Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Command State Machine Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
General Description
The MT28F1284W18 is a high-performance, highdensity, nonvolatile memory solution that can significantly improve system performance. This architecture features a multipartition configuration that supports READ-While-PROGRAM/ERASE operations with no latency. An 8Mb partition size enables optimal design flexibility. A high-performance bus interface enables a fast burst mode READ operation; a conventional asynchronous/page bus interface is provided as well. The burst interface increases the data throughput, minimizing the impact of the first data latency. The MT28F1284W18 enables soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two 64-bit chip protection registers are provided. The embedded WORD PROGRAM and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). An on-chip device status register can be used to monitor the WSM status and determine the progress of the PROGRAM/ERASE tasks. Please refer to Micron's Web site www.micron.com/flash for the latest data sheet. at
Architecture and Memory Organization
The MT28F1284W18 Flash device contains 16 separate partitions (banks) of memory for simultaneous READ and PROGRAM/ERASE operations. Burst READs can cross partition boundaries, but the user must ensure that the burst does not extend into a partition that is actively programming or erasing. During a PROGRAM/ERASE operation, any of the fifteen other partitions may be read. Note that only two partitions can operate simultaneously. Partitions are configured as follows: * Partition 0 (bottom boot) or partition 15 (top boot) contains eight 8K-word parameter blocks and seven 64K-word main blocks. * The other 15 partitions contain eight 64K-word main blocks and comprise one-sixteenth of the total memory. Figure 3 depicts the memory organization.
Figure 2: Functional Block Diagram
PR Lock Query DQ0-DQ15 OTP Manufacturer's ID Data Input Buffer Data Register RST# CE# WE# OE# Device ID Block Lock RCR
CSM
Status Reg.
WSM
Program/ Erase Pump Voltage Generators Output Multiplexer
DQ0-DQ15
I/O Logic
Output Buffer
A0-A22
Address Input Buffer Address CNT WSM Address Multiplexer
Y/Z DEC X DEC
Y/Z Gating/Sensing Bank 0 Blocks
Y/Z DEC X DEC
" "
Y/Z Gating/Sensing Bank 15 Blocks
" "
WAIT#
ADV#
Address Latch
CLK
BSM
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 3: Memory Organization Bottom Boot Block Device
Partition 14 Partition 15 Parameter SIZE(KW) 64 ... BLK# 134 ... 128Mb 7F0000-7FFFFF ... Partition 15
Top Boot Block Device
SIZE(KW) 8 ... BLK# 134 ... 128Mb 7FE000-7FFFFF ... 7F0000-7F1FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF ... 700000-70FFFF 6F0000-6FFFFF ... 680000-68FFFF 670000-67FFFF ... 600000-60FFFF 0F0000-0FFFFF ... 080000-08FFFF 070000-07FFFF ... 000000-00FFFF ... ...
64 64 ...
127 126 ...
780000-78FFFF 770000-77FFFF ...
8 64 ... 64 64 ...
127 126 120 119 ... 112 111 ... 104 103 ... 96 ...... ... 15 ... 8 7 ... 0 ...
64 .... ... 64 64 ...
Partition 12 Partition 13 Partition 14
64
119 ......
680000-68FFFF
...
64 64 ... 64 64 ... 64 64 64 64 ... 64 64 ... 64 ...
Partition 1 Partition 2 Partition 3
38 ...
1F0000-1FFFFF ... 180000-18FFFF 170000-17FFFF ... 100000-10FFFF F00000-0FFFFF ...
64 64 ...
31 30 ... 23 22 ...
64 64 ...
64 64 ...
15 14 ... 8 7 ...
080000-08FFFF 070000-07FFFF 010000-01FFFF 00E000-00FFFF ... ...
Parameter
64 8 ...
8
0
000000-001FFF
NOTE: 1. Total number of blocks: 8 parameter + 127 main = 135.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
Partition 0 Partition 1
Partition 0
..........
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Device Marking
Due to the size of the package, the Micron(R) standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers in Table 1.
Table 1:
Cross-Reference for Abbreviated Device Marking
ENGINEERING SAMPLES
FX616 FX615 FX618 FX617
PRODUCT PART NUMBER
MT28F1284W18FQ-606 TET MT28F1284W18FQ-606 BET MT28F1284W18FQ-705 TET MT28F1284W18FQ-705 BET
QUALIFICATION SAMPLES
FY616 FY615 FY618 FY617
PRODUCTION MARKING
FW616 FW615 FW618 FW617
Part Numbering Information
Micron's low-power devices are available with several different combinations of features (see Figure 4). Valid combinations of features and their corresponding part numbers are listed in Table 2.
Figure 4: Part Number Chart
MT 28F 1284W18 FQ-60 6 M B ET ES
Micron Technology Flash Family
28F = Dual-Supply Flash
Production Status
Blank = Production ES = Engineering Samples QS = Qualification Samples
Density/Organization/Banks
128 = 128Mb (8,192K x 16) 4 = 16 banks (all banks have the same dimensions)
Operating Temperature Range
ET = Extended (-40C to +85C)
Boot Block Starting Address
B = Bottom boot T = Top boot
Read Mode Operation
W = Asynchronous/Page/Burst Read
Operating Voltage Range
18 = 1.70V-1.95V Vcc 1.70V-2.24V VccQ
Manufacturer ID
M = Micron [2Ch]
Package Code
FQ = 56-ball VFBGA (Standard) 7 x 8 grid BQ = 56-ball VFBGA (Lead-free) 7 x 8 grid
Burst Mode Frequency
5 = 54 MHz 6 = 66 MHz
Access Time
-60 = 60ns -70 = 70ns
Table 2:
Valid Part Number Combinations
ACCESS TIME (ns)
60 60 70 70
PART NUMBER MT28F1284W18FQ-606 BET MT28F1284W18FQ-606 TET MT28F1284W18FQ-705 BET MT28F1284W18FQ-705 TET
BOOT BLOCK STARTING ADDRESS
Bottom Top Bottom Top
BURST FREQUENCY (MHz)
66 66 54 54
OPERATING TEMPERATURE RANGE
-40oC to +85oC -40oC to +85oC -40oC to +85oC -40oC to +85oC
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 3: Ball Descriptions
SYMBOL A0-A22 TYPE Input DESCRIPTION Address inputs: Inputs for the addresses during READ and WRITE operations. All addresses are internally latched during WRITE cycles and synchronous READ cycles. During asynchronous READ cycles, A0-A3 are not internally latched. Clock: Synchronizes the Flash device to the system operating frequency during burst mode READ operations. When configured for burst mode READs, address is latched on the first rising (or falling, depending upon the read configuration register setting) CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. CLK is ignored during asynchronous page access READ and WRITE operations.1 Address Valid: Indicates that a valid address is present on the address inputs. Addresses are latched on the rising edge of ADV# during READ operations.1 Chip Enable: Activates the device when LOW. When CE# is HIGH, the device goes into standby power mode if neither PROGRAM nor ERASE operations are pending. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command state machine (CSM) or to the memory array. Reset: When RST# is a logic LOW, the device is in reset mode, which drives the outputs to High-Z and resets the write state machine. When RST# is at logic HIGH, the device is in standard operation. When RST# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Write Protect: Controls the lock down function of the flexible locking feature. Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle during PROGRAM operation. Inputs commands to the command user interface when CE# and WE# are active. DQ0-DQ15 output data when CE# and OE# are active. Wait: Provides data valid feedback during burst read access. The signal is gated by CE#. The WAIT# signal polarity is set by RCR10 in the RCR. Device Power Supply: [1.70V-1.95V] Supplies power for device operation. I/O Power Supply: [1.70V-2.24] Supplies power for input/output buffers. I/O Ground: Do not float any ground ball. Supply Ground: Do not float any ground ball. Program/Erase Enable: [0.9V-1.95V or 11.4V-12.6V] Operates as input at logic levels to control complete device protection. Provides factory programming compatibility, and acts as a current source, when driven to 11.4V-12.6V.
58-BALL FBGA NUMBERS E8, D8, C8, B8, A8, B7, A7, C7, A2, B2, C2, A1, B1, C1, D2, D1, D4, B6, A6, C6, B3, C3, D7 B4
CLK
Input
C4 E7
ADV# CE#
Input Input
F8 C5
OE# WE#
Input Input
B5
RST#
Input
D6 F7, E6, E5, G5, E4, G3, E3, G1, G7, F6, F5, F4, D5, F3, F2, E2 D3 A4, G4 E1, G6 G2, G8 A3, F1 A5
WP# DQ0- DQ15
Input Input/ Output
WAIT# VCC VCCQ VSSQ VSS VPP
Output Supply Supply Supply Supply Supply/ Input
NOTE: 1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous/page mode.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Command State Machine (CSM)
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). Table 5 defines the available commands and provides data for each of the bus cycles, and Table 6 provides the command descriptions. Program and erase algorithms are automated by an onchip WSM. During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. Table 27 shows the CSM transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally to accomplish the requested operation. A command is valid only if the exact sequence is completed. After the WSM completes its task, the WSM status bit (SR7) (see Table 7) is set to a logic HIGH level (VIH), allowing the CSM to respond to the full command set again.
Command State Machine Activation
Device operations are selected by entering an 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os DQ0-DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE# and WE# must be at a logic LOW level (VIL), and OE# and RST# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ, depending upon the command. During a READ operation, control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at logic HIGH (VIH). Table 4 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is reset, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. Users can verify the status of the operations initiated by the CSM by reading the status register. This single status register permits monitoring of the progress of the various operations that can take place on a memory partition. Status register bits SR0-SR7 correspond to DQ0-DQ7 (see Table 7).
Table 4:
MODE
Bus Operations
RST# VIH VIH VIH VIL VIH CE# VIL VIH VIL X VIL ADV# VIL X X X X OE# VIL X VIH X VIH WE# VIH X VIH X VIL WAIT# Active1 High-Z Active High-Z High-Z
1
DQ0-DQ15 DOUT High-Z High-Z High-Z DIN
Read (array, status registers, device identifier, or query) Standby Output disable Reset Write
NOTE: 1. The WAIT# signal is driven by CE#; polarity depends on RCR10. Valid only in synchronous mode only.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 5: Command Sequencing
FIRST BUS CYCLE COMMAND READ ARRAY READ DEVICE IDENTIFIER READ QUERY READ STATUS REGISTER CLEAR STATUS REGISTER BLOCK ERASE SETUP PROGRAM SETUP FAST PROGRAMMING ALGORITHM PROGRAM/ERASE SUSPEND PROGRAM/ERASE RESUME LOCK BLOCK UNLOCK BLOCK LOCK-DOWN BLOCK PROTECTION PROGRAM LOCK PROTECTION PROGRAM SET READ CONFIGURATION REGISTER NOTE: 1. BA: IA: IC: ID: BBA: OPERATION WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE ADDRESS1 PnA PnA PnA PnA XX BA WA WA XX XX BA BA BA PA LPA RCRV DATA FFh 90h 98h 70h 50h 20h 40h/10h 30h B0h D0h 60h 60h 60h C0h C0h 60h SECOND BUS CYCLE OPERATION READ READ READ WRITE WRITE WRITE ADDRESS BBA + IA PBA + QA BA BA WA WA DATA IC QD SRD D0h WD D0h
WRITE WRITE WRITE WRITE WRITE WRITE
BA BA BA PA LPA RCRV
01h D0h 2Fh PD FFFDh 03h
Address within the block. Identification code address. Identifier code data. Identification code data. Block base address. The first address of a particular block. LPA: Lock protection register address (BBA + 80h). PA: Protection register address. PBA: Partition base address. The very first address of a particular partition. PD: Data to be written at location PA.
PnA: Any address within a specific partition. QA: Query code address. QD: Query code data DQ[7:0]. RCRV:Data to be written into the read configuration register presented on A15-A0. SRD: Data read from the status register. WA: Word address of memory location to be written. WD: Data to be written at the location WA. XX: Any valid address within the device.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 6:
OPERATION READ
Command Codes and Descriptions
CODE FFh 70h DEVICE MODE Read Array Read Status Register BUS CYCLE First First DESCRIPTION Places the addressed partition in read array mode. This command places the addressed partition into read status register mode. Reading the partition will output the contents of the status register for the addressed partition. The device will automatically enter this mode for the addressed partition after a PROGRAM or ERASE operation has been initiated. Puts the addressed partition into the read device identifier mode so that reading the device will output the manufacturer/device codes, configuration register data, block lock status, or protection register data on DQ0-DQ15. Puts the addressed partition into the read query mode so that reading the partition will output common flash interface information. The WSM can set the block lock status (SR1), VPP status (SR3), program status (SR4), and erase status (SR5) bits in the status register to "1," but it cannot clear them to "0." SR1, SR3, SR4, and SR5 can only be cleared by a device reset or by using the CLEAR STATUS REGISTER command. A two-cycle command: The first cycle prepares for a PROGRAM operation, and the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. After the second cycle, the device outputs status register data on the falling edge of OE# or CE#, whichever occurs last. Equivalent to Program Setup (40h).
90h
Read Device Identifier
First
98h
Read Query
First
50h
Clear Status Register
First
PROGRAM
40h
Program Setup
First
10h 30h
Program Setup FPA Setup
First First
D0h ERASE 20h
FPA Confirm Erase Setup
D0h
Erase Confirm
SUSPEND
B0h
Program/Erase Suspend
D0h
Program/Erase Resume
This program command activates FPA mode. The first cycle prepares for FPA operation. If the second cycle is an FPA CONFIRM COMMAND (D0h), subsequent WRITEs provide program data. All other commands are ignored once FPA mode begins. Second If the previous command was FPA SETUP (30h), the CSM latches the address and data and prepares the device for FPA mode. First Prepares the CSM for the ERASE CONFIRM command. If the next command is not ERASE CONFIRM, the CSM will set both SR4 and SR5 of the status register to a "1," place the partition into read status register mode, and wait for another command. Second If the previous command was an ERASE SETUP command, then the CSM will close the address and data latches, and it will begin erasing the block indicated on the address pins. The device will then output status register data on the falling edge of OE# or CE#, whichever occurs last. First Issuing this command will suspend the currently executing PROGRAM/ERASE operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6), and the WSM status bit (SR7) to a "1" (ready). The WSM will continue to idle in the suspend state, regardless of the state of all input control signals except RST#, which will immediately reset the WSM and the remainder of the chip if RST# is driven to VIL. First If a PROGRAM or ERASE operation is suspended (as indicated by SR2 or SR6), this command will resume the operation.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 6:
OPERATION BLOCK LOCKING
Command Codes and Descriptions (continued)
CODE 60h 01h D0h DEVICE MODE Block Lock Setup Lock Block Unlock Block BUS CYCLE First DESCRIPTION Prepares the CSM for changes to the block locking status. See note 1.
2Fh PROTECTION PROGRAM C0h
Lock Down Block Protection Register Program Setup
SET READ CONFIGURATION REGISTER
60h
03h
Set Read Configuration Register Setup Set Read Configuration Register Data
Second If the previous command was BLOCK LOCK SETUP, the CSM will latch the address and lock the block indicated on the address bus. Second If the previous command was BLOCK LOCK SETUP, the CSM will latch the address and unlock the block indicated on the address bus. If the block had been previously set to lock down, this operation will have no effect unless WP# is driven to VIH. Second If the previous command was BLOCK LOCK SETUP, the CSM will latch the address and lock down the block indicated on the address bus. First Prepares the CSM for a PROTECTION REGISTER PROGRAM operation. The second cycle latches address and data, and starts the WSM's protection register program or lock algorithm. After the second cycle, the device outputs status register data on the falling edge of OE# or CE#, whichever occurs last. To read array data after programming, issue a READ ARRAY command. First Prepares the RCR to be modified. See note 1.
Second If the previous command was SET READ CONFIGURATION REGISTER SETUP, the configuration bits presented on the address bus will be stored into the Read Configuration Register.
NOTE: 1. If the 60h command is not followed by D0h, 01h, 2Fh, or 03h, the CSM sets SR4 and SR5 to indicate a command sequence error.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Status Register
The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register provides the status of the device to the external microprocessor. During periods when the WSM is active in a partition, that partition will default to the read status register mode and can be polled to determine the WSM status. After monitoring the status register during a PROGRAM/ERASE operation in a partition, that partition will remain in read status mode until a new command is issued to the CSM. Table 7 defines the status register bits.
Clear Status Register
The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, the state of the device does not change.
Table 7:
SR7
Status Register Bit Definitions
DESCRIPTION SR7 indicates ERASE or PROGRAM completion in the device. SR6-SR1 are invalid while SR7 = 0. See Table 8 for valid SR7 and SR0 combinations. When ERASE SUSPEND is issued, WSM halts execution and sets both SR7 and SR6 bits to "1." SR6 bit remains set to "1" until an ERASE RESUME command is issued. When this bit is set to "1," WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word. The VPP status bit does not provide continuous indication of the VPP level. The WSM interrogates the VPP level only after the PROGRAM or ERASE command sequences have been entered and informs the system if VPP is LOW. The VPP level is also checked before the PROGRAM/ERASE is verified by the WSM. When PROGRAM SUSPEND is issued, WSM halts execution and sets both SR7 and SR2 bits to "1." SR2 bit remains set to "1" until a PROGRAM RESUME command is issued. If a PROGRAM or ERASE operation is attempted to a locked block, SR1 is set by the WSM. The operation specified is aborted and the device is returned to read status mode. Addressed partition is erasing or programming. In FPA mode, SR0 indicates a data stream word has finished programming or verifying, depending on the FPA phase. Refer to Table 8 for valid SR7 and SR0 combinations. WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy ERASE SUSPEND STATUS 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/ Completed ERASE STATUS 1 = Error in Block Erasure 0 = Successful BLOCK ERASE PROGRAM STATUS 1 = Error in PROGRAM 0 = Successful PROGRAM VPP STATUS 1 = VPP Low Detect, Operation Abort 0 = VPP = OK
STATUS BIT # STATUS REGISTER BIT
SR6
SR5
SR4
SR3
SR2
SR1
SR0
PROGRAM SUSPEND STATUS 1 = PROGRAM Suspended 0 = PROGRAM in Progress/Completed BLOCK LOCK STATUS 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No Operation to Locked Blocks FAST PROGRAMMING ALGORITHM STATUS 0 = Partition is busy, but only if SR7 = 0 1 = Another partition is busy, but only if SR7 = 0
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Table 8:
SR7 0 0 1 1
Status Register SR7 and SR0 Description
SR0 0 1 0 1 DESCRIPTION The addressed partition is performing a PROGRAM/ERASE operation. FPA: Device is finished programming or verifying data or is ready for data. A partition other than the one currently addressed is performing a PROGRAM/ERASE operation. FPA: the device is either programming or verifying data. No PROGRAM/ERASE operation is in progress in any partition. Erase and program suspend bits (SR6 and SR2) indicate whether other partitions are suspended. Will not occur in standard PROGRAM/ERASE operations. FPA: This combination will not occur.
READ Operations
The following READ operations are available: READ ARRAY, READ DEVICE IDENTIFIER, READ QUERY, and READ STATUS REGISTER. Note that READ DEVICE IDENTIFIER, READ QUERY, and READ STATUS REGISTER will read in either asynchronous or single burst mode.
Read Query
The read query mode outputs common flash interface (CFI) data when the device is read. (See Table 26 on page 59 for more information.) Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0-DQ7. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL) and WE# and RST# must be at a logic HIGH level (VIH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return the addressed partition to read array mode, write the read array command code (FFh) on DQ0-DQ7.
Read Array
The array is read by entering the command code FFh on DQ0-DQ7 to each partition to be read. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL) and WE# and RST# must be at a logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Upon device reset, all partitions default to the read array mode. To return the addressed partition to read array mode, write the read array command code (FFh) on DQ0-DQ7.
Read Status Register
The status register provides the status of the device to the external microprocessor. The status register is read by entering the command code 70h on DQ0-DQ7. The address for both cycles must be in the same partition. Status register data is updated and latched on the falling edge of OE#, on the falling edge of CE#, or on the clock edge which starts a burst (whichever occurs last). See "Burst Read Mode" on page 16 for BURST operation. Latching the data prevents errors from occurring if the register input changes while monitoring the status register. The status register outputs the data on DQ0-DQ7. Table 7 contains the status register definitions. To return the addressed partition to read array mode, write the read array command code (FFh) on DQ0-DQ7.
Read Device Identifier
The read device identifier mode outputs five types of information: the manufacturer and device identifier, the block locking status, the read configuration register, and the protection register data. Two bus cycles are required for this operation: the device identifier data is read by entering the command code 90h on DQ0-DQ7 and the identification code address on the address lines. Control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at a logic HIGH level (VIH) to read device identifier data. Data is available on DQ0-DQ15. To return the addressed partition to read array mode, write the read array command code (FFh) on DQ0-DQ7. See Table 15 on page 36 for more details.
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Read Modes
The MT28F1284W18 supports two read configurations: asynchronous/page mode and burst mode. The RCR15 bit (see Table 9) in the read configuration register sets the read configuration. At reset, asynchronous/ page mode is the default configuration for all READ operations. the partition boundary is reached, and then read from partition 1. If the application keeps clocking beyond partition 15 last location, then the internal counter restarts from partition 0 first address (see Figure 5).
Asynchronous/Page Read Mode
Asynchronous/page read mode is the default read configuration state. To use the device in an asynchronous-only application, ADV# and CLK may be tied to VSS, and WAIT# should be floated. Note that ADV# may also be used in asynchronous mode to latch addresses (latched asynchronous read mode). A random access is initiated either on the falling edge of CE#, on the falling edge of ADV#, or on a transition of the address lines (A0-A22), whichever occurs last. Access times are given by tACE, tAADV, and tAA, respectively. A latched asynchronous read mode is also available in which all address lines except A0-A3 are latched. In this mode, the rising edge of ADV# will latch the addresses. After the addresses are latched, this mode becomes identical to the normal mode. The latched mode is useful when noise is present on the address lines, which might cause a READ operation from unwanted locations. Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. The initial portion of the page mode cycle is the same as the asynchronous access cycle. Subsequent READs are performed by holding CE# LOW and toggling A0-A3, allowing random access of other words in the page. These subsequent READs are done at the faster page access time, tAPA.
Figure 5: Partition Boundary Wrapping (Bottom Boot Example)
Partition 0 start address 00000h
Partition 0 end address Partition 1 start address
07FFFFh 080000h Partition 0 Partition boundary
Partition 1 end address
. . .
0FFFFFh
Partition 15
Partition 15 start address
780000h
Partition 15 end address
7FFFFFh
Burst Read Mode
The burst read mode is used to achieve a faster data rate than is possible with asynchronous read mode. A burst access is started when an active clock edge (defined by RCR6; refer to Table 9 for more information) occurs after ADV# goes LOW. The address is latched when ADV# goes HIGH or on the active clock edge, whichever occurs first. The burst read configuration is set in the read configuration register. BURST READ operations can traverse partition boundaries, but application code is responsible for ensuring that the operations do not extend into partitions that are programming or erasing. All blocks in all partitions are burstable. For example, if a burst starts in partition 0, the application can keep clocking until
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Clock Suspend The clock suspend feature enables the device to suspend a burst sequence, to allow data to be retrieved from another device sharing the same bus. The system processor can resume the burst sequence where it left off at a later time, with zero initial access latency penalty. Clock suspend is most beneficial in non-cached systems. Clock suspend can occur at any stage of a burst, during initial access latency, or when outputting data. When a burst access is suspended, internal array sensing continues, and any previously latched internal data is retained. As long as the device operation conditions are met, a burst sequence can be suspended and resumed without any limit. Clock suspend is executed when CE# is asserted, the current address has been latched (either ADV# rising edge or CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or VIL. To resume, OE# is re-asserted and CLK is restarted. Subsequent CLK edges resume the burst sequence where it left off. Note that when using the clock suspend feature, the device's WAIT# signal remains active. Multiple devices should not share the systems's READY signal when using the clock suspend feature. Refer to the WAIT# signal configuration on RCR8.
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Read Configuration Register (RCR) The SET READ CONFIGURATION REGISTER command is a sequence used to load the read configuration register (RCR). It is a two-cycle command sequence. Read configuration setup (60h) is written, followed by a second WRITE (03h) that specifies the value to be written to the read configuration register. The new RCR settings are placed on the address bus (A0-A15), and are latched on the rising edge of CE# or WE#, whichever occurs first. Refer to Table 9 for the RCR bit settings. After setting the RCR, the device automatically returns to read array mode. Upon reset, the RCR is set to FFCFh.
Table 9:
BIT # 15 14 13-11
Read Configuration Register
DESCRIPTION Read Mode Reserved Latency Code FUNCTION 0 = Synchronous Burst Access Mode 1 = Asynchronous/Page Access Mode (default) Default = 1 Sets the number of clock cycles before valid data out (see Figure 6): 000 = Code 0 - reserved 001 = Code 1 - reserved 010 = Code 2 011 = Code 3 100 = Code 4 101 = Code 5 110 = Code 6 - reserved 111 = Code 7 - reserved (default) 0 = WAIT# signal is active LOW 1 = WAIT# signal is active HIGH (default) Sets the data output configuration: 0 = Hold data for one clock 1 = Hold data for two clocks (default) Controls the behavior of the WAIT# output signal: 0 = WAIT# asserted during delay 1 = WAIT# asserted one data cycle before delay (default) Specifies the order in which data is addressed in synchronous burst mode: 0 = Reserved 1 = Linear (default) Defines the clock edge on which the BURST operation starts and data is referenced: 0 = Falling edge 1 = Rising edge (default) Default = 0 0 = Burst wraps within the burst length 1 = Burst no wrap (default) Sets the number of words the device will output in burst mode: 001 = 4 words 010 = 8 words 011 = 16 words 111 = Continuous burst (default)
10 9
Wait Signal Polarity Hold Data Out
8
Wait Configuration
7
Burst Sequence
6
Clock Configuration
5-4 3 2-0
Reserved Burst Wrap Burst Length
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WAIT# Signal Function When performing a continuous burst, or when performing a four-, eight-, or 16-word burst with no wrap selected (RCR3 = 1), the device may have an output delay when the burst sequence crosses the first 16word boundary. The delay will occur only once during any burst access. The starting address dictates the amount of delay. If the starting address is at the end of a 16-word boundary, the output delay will be the maximum delay. If the starting address is aligned with a 16word boundary, a delay will not be seen. Likewise, if a burst never crosses a 16-word boundary, no delay will be seen. For example, in a four-word burst, no-wrap mode, possible linear burst sequences that do not cause delays are: The WAIT# output is high impedance until the device is active (CE# = VIL). In asynchronous/page mode, WAIT# is set to an asserted state (as defined by RCR10). WAIT# is also set to an asserted state during non-read-array BURST operations such as burst read of status register, query, or device identifier. During clock suspend, WAIT# remains active because CE# gates the WAIT# signal. The WAIT# signal does not revert to a high-impedance state when OE# is de-asserted and therefore can cause contention with another device attempting to control the system's ready signal during a clock suspend. Multiple devices should not be connected directly to the sysem's READY ready signal if the clock suspend feature is used. Read Mode The device supports two read configurations: burst mode, and asynchronous/page mode. The RCR15 bit (refer to Table 9) in the read configuration register sets the read mode. Asynchronous/page mode is the default read mode. Latency Counter The latency counter (RCR13-RCR11) provides the number of clocks that must elapse after the clock edge that starts the burst before data is valid, as shown in Figure 6. This value depends on the input clock frequency. See Table 10 for the clock frequency vs. first access latency information.
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
4-5-6-7 5-6-7-8 6-7-8-9 7-8-9-10
8-9-10-11 9-10-11-12 10-11-12-13 11-12-13-14 12-13-14-15
The WAIT# signal informs the system if an output delay occurs. When the WAIT# signal is asserted, it indicates invalid data. When the WAIT# signal is deasserted, it indicates valid data. See Figure 26 for more details.
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Figure 6: Latency Counter
CLK VIH VIL A0-A21 VIH VIL ADV# VIH VIL VOH DQ0-DQ15 VO L VOH DQ0-DQ15 VO L VOH DQ0-DQ15 VO L Code 5 VOH DQ0-DQ15 VO L VALID OUTPUT VALID OUTPUT Code 4 VALID OUTPUT VALID OUTPUT VALID OUTPUT Code 3 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT Code 2 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID ADDRESS
UNDEFINED
NOTE: CLK shown as rising edge configuration (RCR6 = 1).
Table 10: Clock Frequency vs. First Access Latency
LATENCY COUNTER CODE Frequency (MHz) 2 40 3 54 4/5 66
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WAIT# Signal Polarity RCR10 sets the WAIT# signal polarity. When RCR10 = 0, WAIT# is active LOW. When RCR10 = 1, the WAIT# signal is active HIGH. See "WAIT# Signal Function" on page 18 for more information. Hold Data Out The hold data out (RCR9) specifies for how many clocks data will be held valid. (See Figure 7.)
Figure 7: Hold Data Output Configuration
CLK
WAIT# (RCR8 = 1) tACLK WAIT# (RCR8 = 0) Note 1 Note 1
Hold Data 1 CLK
DQ0-DQ15
WAIT# (RCR8 = 0) tKHTL WAIT# (RCR8 = 1)
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
Note 1
VALID OUTPUT
tACLK
Note 1
Hold Data 2 CLK
DQ0-DQ15
VALID OUTPUT
VALID OUTPUT
NOTE: 1. WAIT# shown active HIGH (RCR10 = 1).
WAIT# Configuration The wait configuration bit (RCR8) controls the WAIT# signal behavior for all burst read modes. It should be set according to the system and CPU characteristics. The WAIT# signal can be configured to assert either during valid data, or one data cycle before data becomes valid (see Figure 6). See "WAIT# Signal Function" on page 18 for more information.
Burst Sequence The burst sequence (RCR7) specifies the ordering of data in burst mode. Linear burst order (RCR7 = 1) is the only burst sequence supported by the device. See Table 11 for more details. Clock Configuration The clock configuration (RCR6) defines the clock edge on which the burst operation starts and data is defined.
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Burst Wrap The burst wrap option (RCR3) determines whether the burst access wraps within the burst length or crosses the burst length boundary. In wrap mode (RCR3 = 0) the four-, eight-, or 16-word access will wrap within the four, eight, or 16 words, respectively. In no-wrap mode (RCR3 = 1), the device operates similarly to a continuous burst. See Table 11 for more details. Burst Length The burst length (RCR2-RCR0) defines the number of words the device outputs. The device supports burst lengths of four words, eight words, 16 words, or continuous burst. When the continuous burst option is selected, the internal address wraps to 000000h after reaching the maximum address.
Table 11: Sequence and Burst Length
STARTING ADDRESS (DEC) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ... ... ... ... ... ... WRAP RCR3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... ... ... ... ... ... ... ... ... 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 ... 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... NO WRAP RCR3 4-WORD BURST LENGTH LINEAR 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-WORD BURST LENGTH LINEAR 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... ... ... ... ... ... 16-WORD BURST LENGTH LINEAR 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8 10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9 11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 ... 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20 6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21 7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22 8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-23 9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-24 10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-25 11-12-13-14-15-16-17-18-19-20-21-22-23-24-25-26 12-13-14-15-16-17-18-19-20-21-22-23-24-25-26-27 13-14-15-16-17-18-19-20-21-22-23-24-25-26-27-28 14-15-16-17-18-19-20-21-22-23-24-25-26-27-28-29 15-16-17-18-19-20-21-22-23-24-25-26-27-28-29-30 CONTINUOUS BURST LINEAR 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... ... ... ... ... ... 14-15-16-17-18-19-20-.. 15-16-17-18-19-20-21-.. ... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... ... ... ... ... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-...
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Programming Operations
In addition to the traditional single word programming commands (10h and 40h), another sequence is offered to speed up the in-factory programming operations (30h). The in-factory programming operation is compatible with the use of an external power supply connected to the VPP ball. For in-system operations, the VPP ball can be connected either to a general purpose I/O ball of the host system, or the VCC ball. READ DEVICE IDENTIFIER, READ QUERY, and READ STATUS REGISTER command until the PROGRAM operation has been completed, after which time, all commands to the CSM become valid again. Taking RST# to VIL during programming aborts the PROGRAM operation, leaving undetermined data in the location being programmed. When programming is aborted, a delay time of tPRD must elapse after RST# goes LOW before the internal RESET operation is complete. An additional delay of tRWH must elapse after RESET is complete (or after RST# goes HIGH, whichever occurs last) before data can be read from the device. Refer to Figure 18 and Table 17 for more information. During programming, VPP must remain above VPPLK, and VCC must remain in the voltage range provided in the recommended operating conditions.
Conventional Word Programming
After the setup command code is entered (10h/40h) on DQ0-DQ7, followed by the data to be programmed, the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The PROGRAM operation may be monitored through the status register. During this time, the CSM will only respond to a PROGRAM SUSPEND, READ ARRAY,
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Figure 8: Conventional Word Programming Flowchart
Start Write 40h, Word Address
BUS OPERATION COMMAND WRITE WRITE PROGRAM SETUP WRITE DATA
COMMENTS Data = 40h Addr = Address of word to be programmed Data = Word to be programmed Addr = Address of word to be programmed Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
WRITE
Write Word Data, Word Address
READ
Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND? PROGRAM SUSPEND Loop
YES
Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
NO SR3 = 0? YES NO SR4 = 0? YES NO SR1 = 0? YES Word Program Passed
BUS OPERATION COMMAND
VPP Range Error
COMMENTS Check SR32 1 = VPP range error Check SR42 1 = Data program error Check SR1 1 = Attempted PROGRAM to locked block. PROGRAM aborted.
READ
Program Error
Lock Block Error
NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR1, SR3, and SR4 are cleared only by the CLEAR STATUS REGISTER command, but do not prevent additional PROGRAM operation attempts.
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Fast Programming Algorithm (FPA) Mode
The fast programming algorithm (FPA) is intended for in-factory use. It enables fast data stream programming. For in-factory programming, FPA minimizes chip programming time when 11.4V < VPP < 12.6V. FPA algorithm can also provide accelerated program with VPP = 1.8V. Executing the FPA command (30h) followed by FPA CONFIRM (D0h), enables an entire block to be programmed. This eliminates the need to continuously update the address to be programmed. An initial delay is required after issuing the FPA command. (See Table 25.) If the block is locked, the status register returns an error. When the FPA command is executed successfully, a data stream can be programmed beginning at the first address. The address can be held constant, or it can be incremented within the address range. The program cycle ends when the programmer writes FFFFh outside the address range of the current block. When the FPA is activated, the data must be provided in sequential order to the WSM. Immediately after programming, verification is executed. The data sequence and starting address are provided to the WSM, which automatically performs a data verification. The result is stored in the status register. Writing FFFFh outside the memory block boundary exits the verification cycle. Figure 9 shows the FPA flowchart. Note that issuing a 70h command to the device after FPA setup (30h) will be interpreted as data and will be written to the device.
Figure 9: Fast Programming Algorithm (FPA) Flowchart (in-factory only)
FPA Setup FPA Program FPA Verify FPA Exit
Start
Read Status Register1
Read Status Register1
Read Status Register1
Unlock Block
SR0 = 1
Data Stream Ready? SR0 = 0 WRITE Data Address = WA4
SR0 = 1
Verify Stream Ready? SR0 = 0 WRITE Data Address = WA4
SR7 = 0
FPA Exited? SR7 = 1 Full Status Check Procedure
WRITE 30h Address = WA4
WRITE D0h Address = WA4
Read Status Register FPA Setup Time SR0 = 1 Read Status Register1 Program Done? SR0 = 0 FPA Setup Done? SR7 = 1 Check VPP and Lock Errors (SR3, SR1) No Last Data? SR7 = 0 Yes WRITE FFFFh Address BA3 No
Read Status Register2 SR0 = 1 Verify Done? SR0 = 0 Last Data? Yes WRITE FFFFh Address BA3
Operation Complete
Exit
NOTE: 1. When reading the status register, the address must be within the block being programmed. 2. During FPA verify, if a word fails to verify, status changes to 90h. 3. BA = Address within block. 4. WA = First word Address to be written in the block.
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ERASE Operations
An ERASE operation must be used to initialize bits in an array block to "1s." The commands to initiate BLOCK ERASE are as follows: BLOCK ERASE SETUP (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Figure 10). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the BLOCK ERASE. During this sequence, the block is programmed with logic 0s, the 0s are then verified, all bits in the block are erased to logic 1 state, and finally verification is performed to ensure that all bits are correctly erased. During an ERASE, VPP must remain above VPPLK, and VCC must remain in the voltage range provided in the recommended operating conditions. Monitoring of the ERASE operation is possible through the status register. SR7 = 1 indicates the ERASE operation is complete. SR5 = 1 indicates an ERASE failure; SR3 = 1 indicates an invalid VPP supply voltage; and SR1 = 1 indicates an ERASE operation was attempted on a locked block. Taking RST# to VIL during an ERASE aborts the ERASE operation leaving undetermined data in the block being erased. When an ERASE is aborted, a delay time of tERD must elapse after RST# goes LOW, before the internal RESET operation is complete. An additional delay of tRWH must elapse after the RESET is complete (or after RST# goes HIGH, whichever occurs last) before data can be read from the device. Refer to Figure 18 on page 38 and Table 17 on page 38 for more information.
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Figure 10: Block Erase Flowchart
Start Issue ERASE SETUP Command and Block Address
BUS OPERATION COMMAND WRITE WRITE ERASE SETUP ERASE
COMMENTS Data = 20h Block Addr = Address within block to be erased Data = D0h Block Addr = Address within block to be erased Status register data Toggle OE# or CE# to update status register Check SR7 1 = Ready, 0 = Busy
WRITE
Issue BLOCK ERASE CONFIRM Command and Block Address
READ
Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 ERASE SUSPEND?
ERASE SUSPEND Loop
YES
BUS OPERATION COMMAND READ
COMMENTS Check SR32 1 = VPP error Check SR4 and SR52 Both = 1 = Command sequence error Check SR52 1 = BLOCK ERASE error
BLOCK ERASE Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
NO SR3 = 0? YES YES SR[4:5] = 1? NO NO SR5 = 0? YES NO SR1 = 0? YES BLOCK ERASE Passed
VPP Range Error
Command Sequence Error
Check SR12 1 = Attempted ERASE of locked block. ERASE aborted. If an error is detected, clear the status register before attempting an erase retry or other error recovery.
Block Erase Error
Lock Block Error
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR1, SR3, SR4, and SR5 are cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. (These bits do not prevent additional ERASE operation.)
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PROGRAM SUSPEND, PROGRAM RESUME, ERASE SUSPEND, ERASE RESUME Commands
During the execution of an ERASE/PROGRAM operation, the SUSPEND command (B0h) can be issued to direct the WSM to suspend the ERASE/PROGRAM operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ DEVICE IDENTIFIER, and PROGRAM RESUME. Additionally, PROGRAM, PROGRAM SUSPEND, ERASE RESUME, LOCK BLOCK, UNLOCK BLOCK, and LOCK DOWN BLOCK are valid commands during an ERASE SUSPEND. (See "Block Locking" on page 30). Once in erase suspend mode, array data must be read/programmed into a block other than the one being erased. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the ERASE/PROGRAM operation, a RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figures 11 and 12). It is also possible that an ERASE in any block can be suspended and a PROGRAM to another block within any partition can be initiated. At this point, a PROGRAM SUSPEND may be issued to allow a READ of yet another location. After the completion of a READ operation, PROGRAM can be resumed by issuing a PROGRAM RESUME command. Finally, after the device has reached the ready state, SR7 = 1, an ERASE RESUME will allow the WSM to finish the original ERASE operation. A minimum time should elapse between an ERASE RESUME command and a subsequent ERASE SUSPEND command to ensure that the device achieves sufficient cumulative erase time.
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Figure 11: Program Suspend/Program Resume Flowchart
Start Issue PROGRAM SUSPEND Command
BUS OPERATION COMMAND WRITE WRITE READ PROGRAM SUSPEND READ STATUS COMMENTS Data = B0h Data = 70h Status register data Toggle OE# or CE# to update status register Check SR7 1 = Ready Check SR2 1 = Suspended Data = FFh Read data from block other than that being programmed Data = D0h
Issue READ STATUS Command Same Partition
WRITE READ MEMORY
Read Status Register Bits
READ
NO SR7 = 1?
WRITE
PROGRAM/ RESUME
NOTE:
YES NO SR2 = 1? YES Full Status Register Check (optional) Program Complete
If the suspended partition was placed in read array mode, then the following condition applies: BUS OPERATION COMMAND WRITE READ STATUS
COMMENTS Return partition to status mode: Data = 70h Addr = address within same partition
Issue READ ARRAY Command
Finish Reading? YES Issue PROGRAM RESUME Command Program Resumed
NO
Write FFh Program Partition
Read Array Data Issue READ STATUS Command
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Figure 12: Erase Suspend/Erase Resume Flowchart
Start Issue ERASE SUSPEND Command
BUS OPERATION COMMAND COMMENTS WRITE WRITE ERASE SUSPEND READ STATUS Data = B0h Data = 70h Addr = Any address in same partition Check SR7 1 = Ready, 0 = Busy Check SR6 1 = Suspended 0 = Completed Data = FFh Addr = Any device address (except block being erased) Read data from, or write data to, a block other than that being erased Data = D0h Addr = Any address
Issue READ STATUS Command Same Partition
WRITE
Read Status Register Bits
READ ARRAY
READ or WRITE
NO
SR7 = 1? YES
WRITE
ERASE RESUME
NOTE:
NO SR6 = 1? YES READ or PROGRAM? READ Issue READ ARRAY Command PROGRAM Loop
(Note 1)
ERASE Complete
If the suspended partition was placed in read array mode or a program loop, then the following condition applies: BUS OPERATION COMMAND COMMENTS WRITE READ STATUS Return partition to status mode Data = 70h Addr = Address within same partition
PROGRAM
NO
READ or PROGRAM Complete?
YES Issue ERASE RESUME Command ERASE Continued2 Issue READ STATUS Command Same Partition
NOTE: 1. See Word Programming flowchart for complete programming procedure. 2. See BLOCK ERASE flowchart for complete erase procedure.
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READ-While-PROGRAM/ERASE Concurrency
It is possible for the device to read from one partition while erasing/programming to another partition. For example, during a READ CONCURRENCY operation, if a PROGRAM or ERASE operation is being performed in partition x, then partition x changes to the read status mode and an array READ operation can be performed on any other partition. Partition x will remain in read status mode. The CFI and the device identifier areas are considered an additional partition separate from the array partitions and support concurrent operations.(See Table 12 for simultaneous operations allowed between the protection register and the main partitions.)
Table 12: Simultaneous Operations Allowed in the Protection Register
PROTECTION REGISTER READ PROGRAM MAIN PARTITION PROGRAM/ERASE READ DESCRIPTION During the programming or erasing of a main partition, the protection register may be read from any other partition. During the programming of the protection register, READs are only allowed in the main partitions. A delay of 200ns must be inserted after issuing the PROTECTION PROGRAM command (C0h) before performing concurrent read of the main partitions.
Block Locking
The Flash device provides a flexible locking scheme that allows each block to be individually locked or unlocked with no latency. The device offers two-level protection for the blocks. The first level allows software-only control of block locking (for data that needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code that does not require frequent updates). Control signals WP#, DQ1, and DQ0 define the state of a block; for example, state [001] means WP# = 0, DQ1 = 0, and DQ0 = 1. See "Reading a Block's Lock Status" on page 33. Table 13 defines all of the possible locking states, Figure 13 shows the block locking state diagram, and Figure 14 describes the locking operations.
Table 13: Block Locking State Transition
WP# 0 0 0 1 1 1 1 DQ1 0 0 1 0 0 1 1 DQ0 0 1 1 0 1 0 1 NAME Unlocked Locked (Default) Lock Down Unlocked Locked Lock Down Disabled Lock Down Disabled ERASE/PROG ALLOWED Yes No No Yes No Yes No LOCK To [001] No Change No Change To [101] No Change To [111] No Change UNLOCK No Change To [000] No Change No Change To [100] No Change To [110] LOCK DOWN To [011] To [011] No Change To [111] To [111] To [111] No Change
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Figure 13: Block Locking State Diagram
UNLOCKED LOCKED
60h/D0h
60h/01h
[000]
60h /2F h
[001]
Power-Up/Reset Default
WP# = VIL = 0
60h/2Fh
[011]
Locked-Down
60h/D0h
60h/01h
[110]
60h/2Fh
[111]
Locked-Down is disabled by WP# = VIH
WP# = VIH = 1
60h/2Fh
Power-Up/Reset Default
60h/D0h
60h/01h
[100]
[101]
60h/D0h = UNLOCK command 60h/01h = LOCK command 60h/2Fh = LOCK DOWN command = WP# hardware control (bidirectional)
= WP# hardware control (unidirectional)
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Figure 14: Locking Operations Flowchart
Start Write 60h, Block Address
Locked State
After a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status register. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the LOCK SETUP command sequence (60h) followed by UNLOCK BLOCK (D0h) can unlock a locked block.
Write 01h/D0h/2Fh, Block Data
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. An unlocked block can be locked or locked down by writing the LOCK SETUP command (60h) followed by LOCK BLOCK (01h), or LOCK DOWN BLOCK (2Fh).
Optional
Write 90h, BA
Read Block Lock Status Lock Change Complete
Locked Down State
The lock down function is dependent on the WP# input. When WP# = 0, blocks in lock down [011] are protected from PROGRAM, ERASE, and lock status changes. When WP# reverts to WP# = 1, the lock down function is disabled [111], and locked down blocks can be individually unlocked by a software command to the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and unlocked [110] as desired while WP# remains HIGH. When WP# goes LOW, blocks that were previously locked down return to the locked down state [011] regardless of any changes made while WP# was HIGH. A locked or unlocked block can be locked down by writing the LOCK SETUP command (60h) followed by LOCK DOWN (2Fh). Resetting the device resets all blocks, including those in lock down, to the locked state (see Table 13).
BUS OPERATION COMMAND WRITE LOCK SETUP
COMMENTS Data = 60h Addr = BLOCK to LOCK/UNLOCK/ LOCK DOWN (BA)
WRITE
LOCK, Data = 01h (LOCK BLOCK) UNLOCK, or D0h (UNLOCK BLOCK) LOCK DOWN 2Fh (LOCK DOWN BLOCK) CONFIRM Addr = BLOCK to LOCK/UNLOCK/ LOCK DOWN (BA) READ ID BLOCK LOCK STATUS Data = 90h Addr = BA Data = Block Lock Status Data Addr = BBA + 02h Confirm locking change on DQ[1:0]. See Table 13 for valid combinations.
WRITE (Optional) READ (Optional)
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Reading a Block's Lock Status
The lock status of every block can be read in the read device identifier mode. To enter this mode, write 90h to the device. Subsequent READs at the base block address +00002 will output the lock status of that block. The lowest two outputs, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/ unlock status and is set by the LOCK command and cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK DOWN command. It can only be cleared by reset or power-down, not by software. Table 13 on page 30 shows the locking state transition scheme and Table 14 shows the write protection truth table. To change a block's lock status during an ERASE operation, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired LOCKING command sequence to the desired block, and the block's lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operations, resume the ERASE operation with the ERASE RESUME command (D0h). If an erase suspended block has its lock status changed, the lock status bits will change immediately. When the ERASE is resumed, the ERASE operation will complete. A locking operation cannot be performed during a PROGRAM SUSPEND. Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Following protection configuration setup (60h), an invalid command will produce a command sequence error (SR4 and SR5 will be set to "1") in the status register. If a command sequence error occurs during an erase suspend, SR4 and SR5 will be set to "1" and will remain at "1" after the erase suspend is resumed. When the ERASE is complete, any possible error during the ERASE cannot be detected via the status register because of the previous command sequence error. This is also true if an error occurs during a program operation error nested within an erase suspend.
Table 14: Write Protection Truth Table
VPP WP# RST# WRITE PROTECTION X VIL X X X X VIL VIH VIL VIH VIH VIH Device inaccessible Word program and block erase prohibited All lock down blocks locked All lock down blocks can be unlocked
Locking Operations During Erase Suspend
Changes to a block's lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress.
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Protection Register
The 128-bit security area is divided into two 64-bit segments. The first 64 bits of the protection register (addresses 81h-84h) are programmed at the factory with a unique 64-bit unchangeable number. DQ0 of the PR lock register (address 80h) is programmed to a "0" state, locking the first 64 bits and preventing any further programming. The second 64 bits (addresses 85h-88h) are left erased for the user to program as desired (see Figure 15). The user can program any information into this area as long as DQ1 of the PR lock register (address 80h) remains unprogrammed. After DQ1 of the PR lock register is programmed, no further programming is allowed in the user area. ERASE operations are not allowed on the protection register. READ-While-PROGRAM operation is only allowed between the chip protection register and main partitions. Table 12 describes the simultaneous operations allowed in the chip protection register.
Figure 15: Protection Register Memory Map
88h
85h 84h
4 Words User-Programmed 4 Words Factory-Programmed
81h 80h
PR Lock
DQ1 DQ0
Reading the Protection Register
The protection register is read in the device identifier mode. To enter this mode, load the 90h command. Once in this mode, READ cycles from addresses shown in Table 15 on page 36 retrieve the specified information. To return to the read array mode, write the READ ARRAY command (FFh).
Programming the Protection Register
The user area of the protection register (addresses 85h-88h) may be programmed by writing the PROTECTION PROGRAM command (C0h), followed by the data to be programmed at one of the addresses within the user area. This procedure may be repeated for each of the addresses in the user area, as long as DQ1 of the PR lock register remains unprogrammed. Issuing a PROTECTION PROGRAM command outside the register's address space results in a status register error (SR4 = 1). See Figure 16 on page 35 for more information.
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Figure 16: Protection Register Programming Procedure
Start Write C0h, Addr = Prot Addr
WRITE BUS OPERATION COMMAND WRITE PROTECTION PROGRAM SETUP COMMENTS Data = C0h Addr = Protection address
Write Protection RegisterAddress/Data
Read Status Register
NO SR7 = 1? YES Full Status Check (if desired)
Data = Data to program Addr = Protection address READ Read SRD Toggle CE# or OE# to update SRD Check SR7 1 = WSM Ready 0 = WSM Busy Protection program operations addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each PROGRAM or after a sequence of PROGRAM operations. BUS OPERATION COMMENTS READ SR1 SR3 SR4 0 1 1 VPP error 0 0 1 Protection register program error 1 0 1 Register locked; operation aborted Only the CLEAR STATUS REGISTER command clears SR1, SR3, and SR4. If an error is detected, clear the status register before attempting a program retry or other error recovery.
Program Complete Read SRD
YES SR3, SR4 = 1? NO YES SR3 = 0, SR4 = 1? NO YES SR1 = 1, SR4 = 1? NO Program Successful
VPP Range Error
Programming Error
Locked-Register Program Aborted
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Locking the Protection Register
DQ0 of the PR lock register is programmed to "0" by the factory to protect the unique device number. DQ1 of the PR lock register can be programmed by the user to lock the user portion (upper 64 bits) of the chip protection register (refer to Figure 15). This bit is set using the PROTECTION PROGRAM command, C0h, to program FFFDh into the PR lock register (address 80h). After DQ1 of the PR lock register is programmed, the user's protection register cannot be changed. The PR lock register will read FFFCh. PROTECTION PROGRAM commands written to a locked section result in a status register error (SR1 = 1, SR4 = 1).
Table 15: Device Identifier Codes
ADDRESS1 ITEM Manufacturer's Identification Code Device ID code Block lock status Block lock down status Read configuration register Protection register lock status Protection register BASE Block Block Block Block Block Block Block OFFSET 00h 01h 02h 02h 05h 80h 81h-84h 85h-88h NOTE: 1. Address = base + offset. DATA 002Ch 44C8h 44C9h DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 Register data Lock data Factory data User data DESCRIPTION Micron ManID 128Mb top boot device 128Mb bottom boot device Block is unlocked Block is locked Block is not locked down Block is locked down
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VPP/VCC Program and Erase Voltages
The Flash device provides in-system programming and erase with VPP in the 0.9V-1.95V range (VPP). The 12V VPP mode programming is offered for compatibility with existing programming equipment. The device can withstand 100,000 PROGRAM/ ERASE operations with VPP = VPP1, or 1,000 PROGRAM/ERASE operations with VPP = VPP2. In addition to the flexible block locking, the VPP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device. When VPP is below VPPLK, any PROGRAM or ERASE operation will result in an error, prompting the corresponding status register bit (SR3) to be set. During PROGRAM and ERASE operations, the WSM monitors the VPP voltage level. PROGRAM/ERASE operations are allowed only when VPP is within the ranges specified in Table 16. When VCC is below VLKO, any PROGRAM/ERASE operation will be disabled. If VCCQ and/or VPP are not connected to the system supply, then VCC should attain VCC (MIN) before applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCC (MIN). Power supply transitions should only occur when RST# is LOW. When VPP is applied within the in-factory programming range (VPP2), the sequence shown in Figure 17 must be followed. Applying VPP within the in-system programming range (VPP1) does not require this sequence.
Figure 17: VCC and VPP at Power Up
VCC VPP 0V 0V T1 > 50s T2 > 1s VPP2
Table 16: VPP Range (V)
SYMBOL VPP1 VPP2 MIN 0.9 11.4 MAX 1.95 12.6
Device Reset
To reset the device, the RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the device defaults to read array mode, the status register is set to 80h, and the read configuration register defaults to asynchronous/page read mode. A delayed access time of tRWH from the rising edge of RST# must elapse before data can be read from the device. The circuitry used to generate the RST# signal needs to be common with the system reset. Refer to the timing diagram for further details. If RST# is asserted during a PROGRAM or ERASE operation, the operation will be aborted and the memory contents at the aborted block or address are invalid.
Standby Mode ICC supply current is reduced by applying a logic HIGH level on CE# to enter the standby mode. In the standby mode, the outputs are at a high impedance state independent of OE#. Applying a logic HIGH level on CE# reduces the current to ICCs. If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete. Automatic Power Save (APS) Mode Substantial power savings are realized during periods when the array is not being read and the device is in active mode. During this time, the device switches to the automatic power save (APS) mode. When the device switches to APS mode, ICC is reduced to a level comparable to ICCS. Further power savings can be realized by applying a logic HIGH level on CE# to place the device in standby mode. The low level of power is maintained until another operation is initiated. In this mode, the I/Os retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control signals toggle.
Power-Up Sequence
The device is protected against accidental block erasure or programming during power transitions. If VCC, VCCQ, and VPP are connected together, it does not matter whether VPP or VCC powers up first.
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Figure 18: Reset Operations
tRP tRWH
A) Reset during read mode
RST#
VIH VIL
tPRD
B) Reset during program or block erase tPRD tRP tERD tRP
RST#
VIH VIL
tERD
Abort Complete
tRWH
tPRD
Abort
tRWH
C) Reset during program or block erase tPRD tRP tERD tRP
RST#
VIH VIL
tERD Complete
DQ0-DQ15
VOH VO L
tVCCRS
VALID OUTPUT
VCC
VCC 0V
Table 17: Reset Parameter Definitions
PARAMETER RST# pulse width RST# HIGH to output delay RST# LOW during PROGRAM to RESET operation complete RST# LOW during BLOCK ERASE to RESET operation complete VCC setup to RST# going HIGH
t t t t
SYMBOL
t
MIN 100
MAX 150 10 20
UNIT ns ns s s s
RP
RWH PRD ERD 60
VCCRS
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Electrical Specificatons Table 18: Absolute Maximum Ratings
Note 1 VOLTAGE Voltage to any ball except VCC, VCCQ, and VPP VPP Voltage VCC Supply Voltage VCCQ Supply Voltage Output Short Circuit Current Operating Temperature Range Storage Temperature Range Soldering Cycle MIN -0.5 -0.2 -0.2 -0.2 -40 -65 MAX +2.45 +14 +2.45 +2.45 100 +85 +125 +260 UNITS V V V V mA C C C NOTES 2
3
NOTE: 1. Stresses greater than those listed in Table 18 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum DC voltage on VPP may overshoot to +14V for periods < 20ns. 3. See technical note TN-00-15, "Recommended Soldering Techniques," for more information.
Table 19: Recommended Operating Conditions
PARAMETER Operating Temperature VCC Supply Voltage I/O Supply Voltage Input/Output Capacitance: DQs VPP Voltage VPP In-factory Programming Voltage Block Erase Cycling (VPP = VPP1) Block Erase Cycling (VPP = VPP2) Time for VPP at VPP2 SYMBOL A VCC VCCQ CIO VPP1 VPP2
T
MIN -40 1.70 1.70 - 0.9 11.4 - -
TYP - - - 4.0 - - - -
MAX +85 1.95 2.24 6.5 1.95 12.6 100,000 1,000 100
UNITS C V V pF V V Cycles Cycles Hours
o
t
PPH
Table 20: Capacitance
TA = +25C; f = 1 MHz PARAMETER/CONDITION Input Capacitance Output Capacitance Clock Capacitance SYMBOL CIN COUT CCLK TYP 5 8 10 MAX 8 10 12 UNITS pF pF pF
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Table 21: DC Characteristics
All currents are in RMS unless otherwise noted VCC = 1.70V-1.95V VCCQ = 1.70V-2.24V PARAMETER Input Low Voltage Input High Voltage Output Low Voltage IOL = 100A Output High Voltage IOH = -100A VPP Lockout Voltage VCC Lock Input Load Current Output Leakage Current VCC Standby Current Asynchronous Read Current @ 5 MHz 4-word Page Read Current @ 13 MHz 8-word Page Read Current @ 13 MHz 16-word Page Read Current @ 13 MHz Vcc Continuous Burst Read Current 4-word Page Read Current @ 54 MHz/66 MHz 8-word Page Read Current @ 54 MHz/66 MHz 16-word Page Read Current @ 54 MHz/66 MHz Continous Burst Read Current @ 54 MHz/66 MHz VCC Program Current VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VCC Block Erase Current VPP = VPP1, Block Erase in Progress VPP = VPP2, Block Erase in Progress VCC Program Suspend Current VCC Erase Suspend Current VCC Automatic Power Save Current VPP Standby Current VPP Program Suspend Current VPP Erase Suspend Current VPP Read Current SYM VIL VIH VOL VOH VPPLK VLKO ILI ILO ICCS ICCR ICCR MIN -0.4 VCCQ - 0.4 -0.1 VCCQ - 0.1 0.4 1.0 0.2 10 5 2 2 2 3 3 3 8 18 8 ICCE 18 8 10 10 10 0.2 0.2 2 30 15 50 50 50 5 5 15 1 1 50 7 4 4 4 5 5 5 12 25 15 mA TYP MAX 0.4 VCCQ + 0.03 0.1 UNITS V V V V V V A A A mA mA NOTES 1 1
2, 3
ICCR
mA
5
ICCW
mA
ICCWS ICCES ICCAPS IPPS IPPWS IPPES IPPR
A A A A A
4 4 4
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 21: DC Characteristics
All currents are in RMS unless otherwise noted VCC = 1.70V-1.95V VCCQ = 1.70V-2.24V PARAMETER VPP Program Current VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VPP Erase Current VPP = VPP1, Erase in Progress VPP = VPP2, Erase in Progress SYM IPPW 0.05 8 IPPE 0.05 8 0.10 22 0.10 22 mA MIN TYP MAX UNITS mA NOTES
NOTE: 1. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. 2. APS mode reduces ICC to approximately ICCS levels. 3. Test conditions: VCC = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. 4. ICCES and ICCWS values are valid when the device is deselected. Any READ operation performed while in suspend mode will have an additional current draw of suspend current (ICCES or ICCWS). 5. ICCR Burst current measurements are made in wrap mode.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 22: Asynchronous READ Cycle Timing Requirements
See Figure 19 and Figure 20 for timing requirements and load configuration. -60 PARAMETER READ cycle time Address to output delay CE# LOW to output delay OE# LOW to output delay RST# HIGH to output delay CE# LOW to output in Low-Z OE# LOW to output in Low-Z CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# transition Address setup to ADV# HIGH CE# LOW to ADV# HIGH ADV# LOW to output delay ADV# pulse width LOW ADV# pulse width HIGH Address hold from ADV# HIGH Page address access
t t t t t t
-70 MAX 60 60 20 150 MIN 70 70 70 30 150 0 0 5 20 0 7 7 60 70 7 7 7 15 22 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SYMBOL
t t
MIN 60
RC
AA
ACE
AOE CEZ OD OH 0 7 7 7 7 7 0 0
RWH
t
t
OEZ
t t t
AVS CVS VP
t
AADV
t
VPH
AVH APA
t
Figure 19: AC Input/Output Reference Waveforms
VCCQ Input VSS VCCQ Input VSS Rise and Fall Levels 10% VCCQ 90% VCCQ VCCQ/2 Test Points VCCQ/2 Output
NOTE: AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Figure 20: Output Load Circuit1
VCCQ 16.7K I/O 16.7K VSS 30pF
NOTE: 1. Minimum recommended capacitive loading is 5pF.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
42
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 23: Burst READ Cycle Timing Requirements
-606 PARAMETER CLK period CLK frequency CLK HIGH (LOW) time CLK fall (rise) time Address valid setup to CLK ADV# LOW setup to CLK CE# LOW setup to CLK CLK to output valid (latency codes 3, 4, and 5) CLK to output valid (latency code 2) Output hold from CLK Address hold from CLK CLK to WAIT# valid CE# LOW to WAIT# valid CE# HIGH to WAIT# High-Z CE# HIGH between subsequent burst READs SYM
t f
-705 MAX MIN 18.5 66 54 6 2 3 7 7 7 11 14 See Note 1 3 7 11 11 11 14 14 14 18 ns ns ns ns ns ns MAX UNITS ns MHz ns ns ns ns ns ns
MIN 15
CLK CLK KP
t
3
tKHKL tAKS tVKS tCKS tACLK tACLK tKOH tAKH tKHTL tCEWV tCEWZ t
7 7 7
See Note 1 3 7
CBPH
14
NOTE: 1. Maximum frequency for latency code 2 = 40 MHz (tACLK = 20ns).
Table 24:
WRITE Cycle Timing Requirements
-60/-70
PARAMETER RST# HIGH recovery to CE# going LOW CE# setup to WE# going LOW Write pulse width Data setup to WE# (CE#) going HIGH Address setup to WE# (CE#) going HIGH CE# hold from WE# HIGH Data hold from WE# (CE#) HIGH Address hold from WE# HIGH Write pulse width HIGH VPP setup to WE# going HIGH VPP hold from valid SRD WP# hold from valid SRD WP# setup to WE# going HIGH WE# HIGH to OE# LOW Write recovery before READ WE# HIGH to output valid WE# HIGH to address valid WE# HIGH to CLK valid WE# HIGH to ADV# HIGH
SYMBOL
tRS tCS tWP t t t t t t
MIN 150 0 40 40 40 0 0 0 20 200 0 0 200 0 50
tAA+20
MAX
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DS AS
CH
DH AH
WPH VPS
t
tVPPH tRHH tRHS tWOA tWOS tWB t
WAV WCV
0 12 12
t
tWAH
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 25: ERASE and PROGRAM Timing Requirements
VPP1 OPERATION Erase Time Suspend Latency PARAMETER
t t
VPP2 TYP 0.25 0.4 5 20 8 0.03 0.24 3.5 15 120 5 5 2.7 1.7 5.6 130 5.6 130 MAX 2.5 4 10 25 130 0.07 0.6 16 UNIT s s s s s s s s ms ms s s s 1, 2 1, 2 NOTES 1, 2 1, 2 1 1 1 1, 2 1, 2
DESCRIPTION
TYP
MAX 2.5 4 10 25
ERS/PB SUSP/P SUSP/E
Erasing and Suspending 0.3 8KW parameter block 64KW main block PROGRAM SUSPEND ERASE SUSPEND 0.7 5 20
ERS/MB
t t
Program Time
t t t
PROG/W
Conventional Word Programming 8 130 Single word 8KW parameter block 64KW main block Single word 0.03 0.24 0.07 0.6 16
PROG/PB
PROG/MB
t t t
Program
FPA/W
Fast Programming Algorithm 3.5 15 120 2.7 1.7
FPA/PB
8KW parameter block 64KW main block FPA Setup Program-to-verify transition Verify
FPA/MB
Operation Latency
t
FPA/SETUP FPA/TRAN
t t
FPA/VERIFY
NOTE: 1. Excludes external system-level overhead. 2. Exact results may vary based on system overhead.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 21: Single Asynchronous READ Operation (Nonlatched Mode)
tRC
A0-A22
VIH VIL
tAA
VALID ADDRESS
CE#
VIH VIL
tACE tAOE tOD
OE#
VIH VIL
tOEZ
tOD
WE#
VIH VIL
tCEZ tOH
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
High-Z
UNDEFINED
READ Timing Parameters
-60 SYMBOL
tRC t
-70 MAX MIN 70 60 60 20 70 70 30 MAX UNITS ns ns ns ns SYMBOL
tCEZ t
-60 MIN 0 0 5 0 0 MAX MIN 0 0
-70 MAX UNITS ns ns 20 ns ns
MIN 60
AA
OEZ
tACE t
tOD t
AOE
OH
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 22: Latched Asynchronous READ Operation
tRC
A3-A22
VIH VIL VIH VIL
VALID ADDRESS
VALID ADDRESS
A0-A3
VALID ADDRESS
tAA tAVS tVPH tAVH
VALID ADDRESS
ADV#
VIH VIL
tVP tAADV tACE
CE#
VIH VIL
tCVS tAOE tOD
OE#
VIH VIL
tOEZ tOD
WE#
VIH VIL
tCEZ
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
tOH
High-Z
UNDEFINED
READ Timing Parameters
-60 SYMBOL
t
-70 MAX MIN 70 60 60 20 150 70 70 30 150 0 0 5 20 MAX UNITS ns ns ns ns ns ns ns ns SYMBOL
t
-60 MIN 0 7 7 60 7 7 7 7 7 7 MAX MIN 0 7 7
-70 MAX UNITS ns ns ns 70 ns ns ns ns
MIN 60
RC
OH
tAA t t t t
tAVS t t t t
ACE AOE RWH CEZ 0 0
CVS AADV VP VPH
tOEZ t
tAVH
OD
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 23: Page Mode READ Operation
A3-A22 VIH VIL VIH VIL VALID ADDRESS
A0-A3
VALID ADDRESS
tAA tAVS tVPH tAVH
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
ADV#
VIH VIL
tVP tAADV tACE
CE#
VIH VIL
tCVS tAOE tOD
OE#
VIH VIL
tOEZ tOD
WE#
VIH VIL
tCEZ
WAIT#
VOH VO L
High-Z Note 1
tAPA tOH
High-Z
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. WAIT# is shown active LOW.
READ Timing Parameters
-60 SYMBOL
tAA t
-70 MAX 60 60 30 150 MIN MAX 70 70 30 150 0 0 5 20 0 UNITS ns ns ns ns ns ns ns ns SYMBOL
tAVS t
-60 MIN 7 7 60 7 7 7 15 7 7 7 MAX MIN 7 7
-70 MAX UNITS ns ns 70 ns ns ns ns 22 ns
MIN
ACE
CVS
tAOE t
tAADV t
RWH 0 0
VP
tCEZ t t t
tVPH t t
OEZ OD OH
AVH APA
0
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 24: Single Burst READ Operation
tCLK
CLK
VIH VIL
tAKS
Note 1
tAKH tKP tKP
A0-A22
VIH VIL
tVPH
VALID ADDRESS
tAVS tVKS tAVH
ADV#
VIH VIL VIH VIL VIH VIL
tCKS tOEZ tOD tVP tCEWZ
CE#
tCVS
tAOE
OE#
WE#
VIH VIL
tCEWV High-Z tOD
WAIT#
VOH VOL
Note 2
tACLK tKOH
High-Z
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
tOH
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
tAOE t t t t t t
-705 MIN MAX 30 0 5 20 0 7 7 7 7 7 18.5 7 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tVKS t
t
-606 MIN 7 7
1
-705 MIN 7 7 11 20 14 20 3 7 TBD TBD 14 14 ns ns ns ns MAX UNITS ns ns ns
MIN
MAX 20
MAX
OEZ OD OH AVS CVS VP
0
CKS
ACLK
0 7 7 7 7 7 15 7
tACLK2
t t t t
KOH AKH CEWV CEWZ
3 7
tVPH t
AVH
tCLK t
AKS
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 25: READ Timing Parameters for Four-Word BURST Operation
tCLK
CLK
VIH VIL
tAKS tAKH
Note 1
tKP tKP
A0-A22
VIH VIL
VALID ADDRESS
tAVS tVPH tVKS tAVH
ADV#
VIH VIL VIH VIL
tCVS tAOE tVP
tCBPH
CE#
OE#
VIH VIL
tCKS
tOD
tOEZ
tOD
WE#
VIH VIL
tCEZ
tKHTL
tOH
WAIT#
VOH VOL
High-Z
Note 2
tACLK tKOH
High-Z
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
t
-705 MIN MAX 30 0 0 5 20 0 7 7 7 7 7 18.5 7 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
t
-606 MIN 7 7
1
-705 MIN 7 7 11 20 14 20 3 7 11 14 18 ns ns ns ns MAX UNITS ns ns ns
MIN
MAX 20
MAX
AOE 0 0
VKS
tCEZ t
tCKS
t t
OEZ
ACLK
tOD t t t t
ACLK2
OH AVS CVS VP
0 7 7 7 7 7 15 7
tKOH t t t
3 7
AKH KHTL CBPH
14
tVPH t
AVH
tCLK t
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
AKS
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 26: WAIT# Functionality for End-of-Word Line (EOWL) Condition
CLK VIH VIL
tAKS tAKH
Note 1
A0-A22
VIH VIL
VALID ADDRESS
tAA tAVS tVPH tVKS
tAVH
ADV#
VIH VIL VIH VIL
tVP tAADV tACE
CE#
OE#
VIH VIL
tCVS
tAOE
tCKS
VIH WE# VIL WAIT# VOH VOL High-Z
tCEWV
tCEZ
tOEZ
tKHTL
Note 2
tACLK tKOH
High-Z
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
tAA t
-705 MIN MAX 70 70 30 0 0 7 7 60 70 7 7 7 7 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tVKS t
t
-606 MIN 7 7 11 20 3 7 11 TBD 3 7 MAX MIN 7 7
-705 MAX UNITS ns ns 14 20 ns ns 14 14 ns ns ns
MIN
MAX 60 60 20
ACE 0 0 7 7
CKS
tAOE t t t t
ACLK1
CEZ OEZ AVS CVS
tACLK2
t t t t
KOH AKH KHTL CEWV
tAADV t
VP
7 7 7 7
tVPH t
AVH
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
tAKS
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 27: WAIT# Signal in Burst Non-READ ARRAY Operation
CLK VIH VIL
tAKS tAKH
Note 1
A0-A22
VIH VIL
VALID ADDRESS
tAVS tVPH tVKS tAVH
ADV#
VIH VIL
tVP
CE#
VIH VIL
tCVS tAOE tOD
OE#
VIH VIL
tCKS
WE#
VIH VIL High-Z
tCEZ
tOEZ
tOD
WAIT#
VOH VOL
High-Z
Note 2
tACLK tOH tKOH
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
tAOE t
-705 MIN MAX 30 0 0 5 20 0 7 7 7 7 7 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL
tAKS t
-606 MIN 7 7 7 11 20 3 7 3 7 MAX MIN 7 7 7
-705 MAX UNITS ns ns ns 14 20 ns ns ns
MIN
MAX 20
CEZ
0 0
VKS
tOEZ t
tCKS
tACLK1 t
OD 0 7 7 7 7 7
tOH t t t t
ACLK2
AVS CVS VP VPH
tKOH t
AKH
tAVH
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 28: WAIT# Signal in Asynchronous READ Operation
tRC
A0-A22
VIH VIL
tAA
VALID ADDRESS
CE#
VIH VIL
tACE
tAOE
tOD
OE#
VIH VIL
tOEZ
tOD
WE#
VIH VIL
tCEZ
WAIT#
VOH VOL
High-Z Note 1
High-Z
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
tOH
High-Z
UNDEFINED
NOTE: 1. WAIT# shown active LOW.
READ Timing Parameters
-60 SYMBOL
t t t t
-70 MAX MIN 70 60 60 20 70 70 30 MAX UNITS ns ns ns ns SYMBOL
t t t t
-60 MIN 0 0 5 0 0 MAX MIN 0 0
-70 MAX UNITS ns ns 20 ns ns
MIN 60
RC AA ACE AOE
CEZ OEZ OD OH
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 29: Two-Cycle WRITE Operation
Note 1 A0-A22 VIH VIL VALID ADDRESS
tAS tAH
VALID ADDRESS
tWAV tAVS
VALID ADDRESS
tAVH
ADV#
VIH VIL
tVP tWAH
CE# (WE#)
VIH VIL
tCS tCH
OE#
VIH VIL
tWP tWPH tWOS
WE# (CE#)
VIH VIL
tRS tDH tWB
DQ0-DQ15
VIH VIL VIH
High-Z
DATA IN
High-Z
DATA IN
tDS
High-Z
VALID SRD
High-Z
RST#
VIL VIH
tRHS
tRHH
WP#
VIL VVPPH
tVPS
tVPPH
VPP VPPLK VIL
UNDEFINED
NOTE:
1. Status register data (SRD) may be read after a two-cycle PROGRAM/ERASE sequence to determine completion of the PROGRAM/ERASE algorithm.
READ/WRITE Timing Parameters
-60/-70 SYMBOL
t t t t
-60/-70 MAX UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL
t t t t
MIN 150 0 40 40 40 0 0 0 7 7
MIN 20 7 200 0 0 200 50
t
MAX
UNITS ns ns ns ns ns ns ns ns ns ns
RS CS WP DS
WPH VP VPS VPPH
tAS t
tRHH t
CH
RHS
tDH t
tWOS t
AH
WB
AA + 20 0 12
tAVH t
tWAV t
AVS
WAH
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 30: Clock Suspend
VIH CLK VIL
tCLK tAKS tKP tKP tAKH
VIH A0-A22 VIL
tVPH
VALID ADDRESS
tAVS tVKS
tAVH
VALID ADDRESS
ADV#
VIH VIL
tVP tCBPH
CE#
VIH VIL
tCVS tCEZ tAOE tOD
OE#
VIH VIL
tCKS tOEZ
tOD tAOE
WE#
VIH VIL
tKHTL
tOH
WAIT#
VOH VOL
High-Z
High-Z
tACLK
tKOH
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
High-Z
High-Z
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
READ Timing Parameters
-606 SYMBOL
t
-705 MIN MAX 30 0 0 5 20 0 7 7 7 7 7 18.5 6 2 3 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
t
-606 MIN 7 7 7 11 20 3 7 11 14 18 3 7 MAX MIN 7 7 7
-705 MAX UNITS ns ns ns 14 20 ns ns 14 ns ns ns
MIN
MAX 20
AOE 0 0
AKS
tCEZ t
tVKS t
OEZ
CKS
tOD t
tACLK1 tACLK2
OH
0 7 7 7 7 7 15 3
tAVS t t t t
t
KOH
CVS VP VPH AVH
tAKH t t
KHTL CBPH
tCLK t
KP
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
tKHKL
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 31: Asynchronous READ-to-WRITE Operation
tRC tAA tAS tAH
A0-A22
VIH VIL VIH VIL
VALID ADDRESS
tACE tOD
VALID ADDRESS
CE#
tAOE
tOD
OE#
VIH VIL VIH VIL
tCEZ tOEZ tOH tDS tDH tCS
tWP
tCH
WE#
DQ0-DQ15
VOH VO L
High-Z
VALID OUTPUT
High-Z
DATA IN
High-Z
UNDEFINED
READ Timing Parameters
-60 SYMBOL
t t t t
WRITE Timing Parameters
-70 -60/-70 MAX UNITS ns 70 70 30 ns ns ns ns ns 20 ns ns SYMBOL
t t t t
MIN 60
MAX
MIN 70
MIN 0 40 40 40 0 0 0
MAX
UNITS ns ns ns ns ns ns ns
RC AA ACE AOE
CS WP DS AS
60 60 20 0 0 5 0 0 0 0
tCEZ t
tCH t
OEZ
DH
tOD t
tAH
OH
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 32: WRITE-to-Asynchronous-READ Operation
tAS tAH tRC
A0-A22
VIH VIL VIH VIL
tCS
VALID ADDRESS
tCH
VALID ADDRESS
tOH
CE#
tWP
tWAV
VIH WE# VIL VIH OE# VIL
tAOE tAA tDS tDH tACE tOD tOD tWOA
DQ0-DQ15
VOH VO L VIH
tRS
High-Z
DATA IN
High-Z
VALID OUTPUT
High-Z
RST#
VIL
UNDEFINED
READ Timing Parameters
-60 SYMBOL
t
WRITE Timing Parameters
-70 -60/-70 MAX UNITS ns 70 70 30 20 ns ns ns ns ns SYMBOL
t
MIN 60
MAX
MIN 70
MIN 150 0 40 40 40 0 0 0 0 0
MAX
UNITS ns ns ns ns ns ns ns ns ns ns
RC
RS
tAA t
60 60 20 5 0 0
tCS t
ACE
WP
tAOE t t
tDS t t t t
OD OH
AS CH DH AH
tWOA t
WAV
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 33: Burst READ-to-WRITE Operation
tAKS tAKH
Note 1
tWAV
CLK
tAVS tAS
A0-A22
tVPH
VALID ADDRESS
tAVH
VALID ADDRESS
VALID ADDRESS
tAH
tVKS
ADV#
tCKS tCVS tCBPH
tCH
CE#
tAOE tOD
OE#
tCS tWP tWPH
WE#
tKHTL
WAIT#
tCEZ tOEZ tACLK tKOH tDS tDH
DQ0-DQ15
High-Z
High-Z
VALID OUTPUT
High-Z
DATA IN
High-Z
DATA IN
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
READ Timing Parameters
-606 SYMBOL
t t t t t t t
WRITE Timing Parameters
-705 -60/-70 UNITS
ns ns
MIN
0 0
MAX
20
MIN
0 0
MAX
30
SYMBOL
t t
MIN 0 40 40 40 0 0 0 0 20
MAX
UNITS ns ns ns ns ns ns ns ns ns
AOE CEZ OEZ OD AVS CVS VPH 7 7 7 7 7 7 7
CS WP
tDS
5 7 7 7 7 7 7 7
20
t
AS
tCH t
DH
tAVH tAKS t t
ns ns ns ns
tAH t t
WAV WPH
VKS CKS
tACLK1 tACLK2 tKOH tAKH t t
11 20
3 7 11 14 18 3 7
14 20
ns
ns ns
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
KHTL CBPH
14
ns ns
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 34: Write-to-BURST READ Operation
tVKS tAKS
Note 1
CLK
tAS
tAH tAKH
A0-A22
VALID ADDRESS
tWAH tVP
VALID ADDRESS
tAVH
ADV#
tCS
tCH
tCBPH
tCKS
CE#
tWAV
tWP
tWCV
WE#
tAOE
OE#
tKHTL
WAIT#
tDS tDH
tACLK
tACLK tKOH
DQ0-DQ15
tRS
High-Z
DATA IN
VALID OUTPUT
VALID OUTPUT
RST#
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
READ Timing Parameters
-606 SYMBOL
tAOE t
WRITE Timing Parameters
-705 -60/-70 UNITS ns ns ns ns ns ns 14 20 ns ns ns 14 ns ns SYMBOL
tRS t
MIN
MAX 20
MIN
MAX 30
MIN 150 0 40 40 40 0 0 0 0 12 12
MAX
UNITS ns ns ns ns ns ns ns ns ns ns ns
VP
7 7 7 7 7
1
7 7 7 7 7 11 20
CS
tAVH t
tWP t
AKS
DS
tVKS t
t
tAS t t t t
CKS
CH DH AH WAV
ACLK
tACLK2
t t
KOH AKH
3 7 11 14
3 7
tWCV t
tKHTL t
WAH
CBPH
18
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Appendix A: CFI Table Table 26: CFI
OFFSET 00 002C 0089 01 44C8 44C9 reserved 0051, 0052 0059 0003, 0000 0039, 0000 0000, 0000 0000, 0000 0017 0019 00B4 00C6 0003 0000 000A 0000 0004 0000 0002 0000 0018 0001 0000 0000, 0000 0002 007E, 0000 0007, 0000 0000, 0002 0040, 0000 0007, 0000 007E, 0000 0040, 0000 0000, 0002 0000, 0000 0000, 0000 0050, 0052 DATA DESCRIPTION Manufacturer's ID (ManID) Micron Intel Device ID Code (DevID) Top boot block device code (Micron) Bottom boot block device code (Micron) Reserved "QR" "Y" Primary OEM command set Address for primary extended table Alternate OEM command set Address for OEM extended table VCC MIN for Erase/Write; Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD VCC MAX for Erase/Write; Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD VPP MIN for Erase/Write; Bit 7-bit 4 volts in hex; Bit 3-bit 0 100mV in BCD VPP MAX for Erase/Write; Bit 7-bit 4 volts in hex; Bit 3-bit 0 100mV in BCD Typical timeout for single byte/word program, 2ns, 0000 = not supported Typical timeout for maximum size multiple byte/word program, 2ns, 0000 = not supported Typical timeout for individual block erase, 2nms, 0000 = not supported Typical timeout for full chip erase, 2ns, 0000 = not supported Maximum timeout for single byte/word program, 2ns times typical, 0000 = not supported Maximum timeout for maximum size multiple byte/word program, 2ns, 0000 = not supported Maximum timeout for individual block erase, 2ns, 0000 = not supported Maximum timeout for full chip erase, 2ns, 0000 = not supported Device size, 2n bytes Bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3 Flash device interface description 0000 = async Maximum number of bytes in multibyte program or page, 2n Number of erase block regions within device (8K words and 64K words) Top boot block device erase block region information 1 Bottom boot block device erase block region information 1 Top boot block device erase block region information 1 Bottom boot block device erase block region information 1 Top boot block device erase block region information 2 Bottom boot block device erase block region information 2 Top boot block device erase block region information 2 Bottom boot block device erase block region information 2 Reserved for future erase block region information Reserved for future erase block region information "PR"
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
02 - 0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A, 2B 2C 2D, 2E 2F, 30 31, 32 33, 34 35, 36 37, 38 39, 3A
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET 3B 3C 3D 3E 3F 40 41 DATA 0049 0031 0033 00E6 0003 0000 0000 DESCRIPTION "I" Major version number, ASCII Minor version number, ASCII Optional Feature And Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = yes = 1 Bit 9 Simultaneous operation supported = yes = 1 Program supported after erase suspend = yes Bit 0 block lock status active = yes; Bit 1 block lock down active = yes VCC supply optimum, 00 = not supported, Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD VPP supply optimum, 00 = not supported, Bit 7-bit 4 volts in BCD; Bit 3-bit 0 100mV in BCD Number of protection register fields in JEDEC ID space Lock bytes LOW address, lock bytes HIGH address 2n factory programmed bytes, 2n user programmable bytes Page mode read capability, 2n bytes Number of synchronous mode read configuration fields that follow Synchronous mode read capability configuration 1 Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Number of device hardware partition regions within the device Number of identical partitions within the partition region Number of identical partitions within the partition region Number of PROGRAM/ERASE operations allowed in a partition Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in program mode Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in erase mode Types of erase block regions in this partition region Partition region 1 erase block type 1 information Partition region 1 erase block type 1 information Partition region 1 erase block type 1 information
42 43, 44 45 46 47 48, 49 4A, 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B
0001 0003, 0000 0018 00C0 0001 0080, 0000 0003, 0003 0005 0004 0001 0002 0003 0007 Top: 0002 Bot: 0002 Top: 000F Bot: 0001 Top: 0000 Bot: 0000 Top: 0011 Bot: 0011 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Top: 0001 Bot: 0002 Top: 0007 Bot: 0007 Top: 0000 Bot: 0000 Top: 0000 Bot: 0040
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET 5C 5D 5E 5F 60 DATA Top: 0002 Bot: 0000 Top: 0064 Bot: 0064 Top: 0000 Bot: 0000 Top: 0001 Bot: 0001 Top: 0003 Bot: 0003 Bot: 0006 Partition region 1 erase block type 2 information Bot: 62 Bot: 63 Bot: 64 Bot: 65 Bot: 66 Bot: 67 Bot: 68 Top: 61 Bot: 69 Top: 62 Bot: 6A Top: 63 Bot: 6B Top: 64 Bot: 6C Top: 65 Bot: 6D Top: 66 Bot: 6E Top: 67 Bot: 6F Top: 68 Bot: 70 Top: 69 Bot: 71 Bot: 0000 Partition region 1 erase block type 2 information Bot: 0000 Partition region 1 erase block type 2 information Bot: 0002 Partition region 1 (erase block type 2) Bot: 0064 Partition region 1 (erase block type 2) Bot: 0000 Partition region 1 (erase block type 2) bits per cell Bot: 0001 Partition region 1 (erase block type 2) page mode and synchronous mode capabilities Bot: 0003 Top: 0001 Bot: 000F Top: 0000 Bot: 0000 Top: 0011 Bot: 0011 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Top: 0002 Bot: 0001 Top: 0006 Bot: 0007 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Number of identical partitions within the partition region Number of identical partitions within the partition region Number of PROGRAM/ERASE operations allowed in a partition Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in program mode. Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in erase mode. Types of erase block regions in this partition region Partition region 2 erase block type 1 information Partition region 2 erase block type 1 information Partition region 2 erase block type 1 information DESCRIPTION Partition region 1 erase block type 1 information Partition 1 (erase block type 1) Partition 1 (erase block type 1) Partition 1 (erase block type 1) bits per cell; internal ECC Partition 1 (erase block type 1) page mode and synchronous mode capabilities Partition region 1 erase block type 2 information Bot: 61
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
61
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET Top: 6A Bot: 72 Top: 6B Bot: 73 Top: 6C Bot: 74 Top: 6D Bot: 75 Top: 6E Bot: 76 Top: 6F Top: 70 Top: 71 Top: 72 Top: 73 Top: 74 Top: 75 Top: 76 77 78 DATA Top: 0002 Bot: 0002 Top: 0064 Bot: 0064 Top: 0000 Bot: 0000 Top: 0001 Bot: 0001 Top: 0003 Bot: 0003 Top: 0007 Top: 0000 Top: 0040 Top: 0000 Top: 0064 Top: 0000 Top: 0001 Top: 0003 DESCRIPTION Partition region 2 erase block type 1 information Partition 2 (erase block type 1) Partition 2 (erase block type 1) Partition 2 (erase block type 1) bits per cell Partition 2 (erase block type 1) page mode and synchronous mode capabilities Partition region 2 erase block type 2 information Partition region 2 erase block type 2 information Partition region 2 erase block type 2 information Partition region 2 erase block type 2 information Partition 2 (erase block type 2) Partition 2 (erase block type 2) Partition 2 (erase block type 2) bits per cell Partition 2 (erase block type 2) page mode and synchronous mode capabilities TBD Reserved
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
Appendix B: CSM Table Table 27: Command State Machine Transition
Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a time.
DEVICE NEXT STATE AFTER COMMAND INPUT BLOCK ERASE CONFIRM, PROGRAM/ ERASE RESUME, UNLOCK BLOCK CONFIRM9 (D0h)
CURRENT CHIP STATE8
READ ARRAY3 (FFh)
PROGRAM SETUP4,5 (10h/40h)
ERASE SETUP4,5 (20h)
FPA SETUP4 (30h)
PROGRAM/ ERASE SUSPEND (B0h)
READ STATUS (70h)
CLEAR STATUS REGISTER 6 (50h)
READ ID/ QUERY (90h, 98h)
LOCK, UNLOCK, LOCK DOWN, RCR SETUP5 (60h)
OTP SETUP5 (C0h)
LOCK BLOCK CONFIRM9 (01h)
LOCK DOWN BLOCK CONFIRM9 (2Fh)
WRITE RCR CONFIRM9 (03h)
FPA EXIT (ADDRESS <> BA) (FFFFh)
ILLEGAL COMMANDS OR FPA DATA (OTHER CODES)2
WSM OPERATION COMPLETES
READY LOCK/RCR SETUP SETUP OTP BUSY SETUP PROGRAM BUSY SUSPEND SETUP BUSY ERASE SUSPEND
Ready
Program Setup
Erase Setup
FPA Setup Ready
Ready Ready (Lock Error)
Lock/RCR Setup
OTP Setup Ready
Ready Ready (Lock Error) N/A
Ready (Lock Error)
OTP Busy Ready Program Busy Program Busy Program Suspend Ready (Error) Erase Busy Program in Erase Suspend Setup Program Busy Erase Busy Erase Suspend Lock/RCR Setup in Erase Suspend Program Suspend Program Busy Program Suspend N/A Ready (Error) N/A Ready
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Erase Busy
Ready
63
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003, Micron Technology, Inc.
Erase Suspend
Erase Suspend
Erase Busy
Erase Suspend
Erase Suspend N/A
SETUP
Program in Erase Suspend Busy Program Suspend in Erase Suspend Program in Erase Suspend Busy Erase Suspend FPA Busy FPA Busy7 Verify Busy7 Erase Suspend (Lock Error) Ready (Error) FPA Verify Ready FPA Busy7 FPA Verify7 Ready Erase Suspend
PROGRAM IN ERASE SUSPEND
BUSY
Program in Erase Suspend Busy
Program in Erase Suspend Busy
SUSPEND
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend
N/A
LOCK/RCR SETUP IN ERASE SUSPEND SETUP FAST PROGRAMMING ALGORITHM FPA BUSY FPA VERIFY
Erase Suspend (Lock Error) Ready (Error)
Erase Suspend
Erase Suspend (Lock Error) N/A
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
Table 27: Command State Machine Transition (continued)
Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a time.
DEVICE NEXT STATE AFTER COMMAND INPUT BLOCK ERASE CONFIRM, PROGRAM/ ERASE RESUME, UNLOCK BLOCK CONFIRM9 (D0h)
CURRENT CHIP STATE8
READ ARRAY3 (FFh)
PROGRAM SETUP4,5 (10h/40h)
ERASE SETUP4,5 (20h)
FPA SETUP4 (30h)
PROGRAM/ ERASE SUSPEND (B0h)
READ STATUS (70h)
CLEAR STATUS REGISTER 6 (50h)
READ ID/ QUERY (90h, 98h)
LOCK, UNLOCK, LOCK DOWN, RCR SETUP5 (60h)
OTP SETUP5 (C0h)
LOCK BLOCK CONFIRM9 (01h)
LOCK DOWN BLOCK CONFIRM9 (2Fh)
WRITE RCR CONFIRM9 (03h)
FPA EXIT (ADDRESS <> BA) (FFFFh)
ILLEGAL COMMANDS OR FPA DATA (OTHER CODES)2
WSM OPERATION COMPLETES
OUTPUT NEXT STATE AFTER COMMAND INPUT1 PROGRAM SETUP, ERASE SETUP, OTP SETUP, PROGRAM IN ERASE SUSPEND SETUP, FPA SETUP, FPA BUSY, VERIFY BUSY LOCK/RCR SETUP, LOCK/RCR SETUP IN ERASE SUSPEND OTP BUSY READY, PROGRAM BUSY, PROGRAM SUSPEND, ERASE BUSY, ERASE SUSPEND, PROGRAM IN ERASE SUSPEND BUSY, PROGRAM SUSPEND IN ERASE SUSPEND
Status
Status Status Array3 Output does not change
Array
Status Output does not change
Status
Output does not change
Status
Status ID/ Query
Status
Output does not change
Array
Output does not change
NOTE: 1. The output state shows the type of data that appears at the outputs if the block address is the same as the command address.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
64
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003, Micron Technology, Inc.
2. Illegal commands are those not defined in the command set. 3. All blocks default to read array mode at power up. 4. Both cycles of two-cycle commands should be issued to the same block address. If they are issued to different blocks, the second WRITE determines the active block. 5. If the CSM is active, both cycles of a two-cycle command are ignored. 6. The CLEAR STATUS command clears the status register error bits except when the CSM is running or during SUSPEND. 7. FPA writes are allowed only when SR0 = 0. FPA is busy if BA = address at FPA CONFIRM command. Any other commands are treated as data. 8. The current state is that of the WSM, not the block. 9. Confirm commands perform the operation and the move to the ready state.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 35: 56-Ball VFBGA
0.10 C 0.700 0.075
SEATING PLANE C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR 96.5% Sn, 3% Ag , 0.5% Cu 5.25 SUBSTRATE: PLASTIC LAMINATE BALL A1 ID MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID BALL A1 4.50 0.05
56X O 0.375 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE-REFLOW BALL DIAMETER IS 0.35 ON A 0.30 SMD BALL PAD.
0.75 TYP
BALL A8 4.50 2.25 0.05 0.75 TYP 9.00 0.10
1.00 MAX 2.625 0.050 11.00 0.10 5.50 0.05
NOTE: 1. All dimensions in millimeters.
Data Sheet Designation
Production: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc
65
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Revision History
Rev. D, Production .........................................................................................................................................................11/03 Updated Vcc and VCCQ MINs Updated DC Table Updated CFI Table Removed TBDs from Timing Table Rev. C, Production .........................................................................................................................................................10/03 Added Lead-free package Updated DC Table Updated Erase and Program Timing Tables Updated CFI Table Rev. B, Advance ................................................................................................................................................................8/03 * Removed support for the "Interleaved" Burst Option * Expanded definition for tACLK * Updated VFBGA package drawing and notes * Added value for tCEWV and tCEWZ Original document, Rev A., Advance .............................................................................................................................3/03
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
66
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc.

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